The current trend in integrated circuit packaging is to use automated forms of lead bonding such as tape automated bonding (TAB) and flip-chip techniques as opposed to the more traditional methods of wire-bonding because of improved reliability, higher yield and improved performance due to the reduced lead inductance, especially for fast chips with large numbers of input/outputs (I/Os).
As future needs for more compact and lightweight packaging become critical for many applications, the present method of single-chip packaging will be replaced by some type of multichip packaging. Of the multichip packaging approaches, the most commonplace is one that uses copper as the conductive metal, polyimide as the dielectric and silicon wafers as substrates, sometimes being referred to as silicon-on-silicon hybrid wafer scale integration. Such a multichip package can either be put into a hybrid ceramic package or mounted directly on some form of mother board. In either case, a problem arises when the number of inputs/outputs (I/Os) of the multichip module is very large (more than a few hundred).
The present invention encompasses ways of facilitating and improving the bonding of a large number of I/Os in a multichip module. The methods of the present invention involve creating feedthroughs in a silicon substrate (e.g., a silicon wafer) using an etching method, as described in greater detail herein.
The following patents involve related technology:
Chatterjee et al. in U.S. Pat. No. 4,695,872, describes a form of multichip packaging. The substrate used in this patent is silicon and its basic form has a processor chip on one side of the substrate with a number of memory chips on the other side. To interconnect the processor chip with the memory chips on the other side of the substrate, Chatterjee et al. creates conduits, i.e., feedthroughs, in the substrate. In contrast to the present methods, the feedthroughs in Chatterjee et al. were created with a laser. Moreover, the subsequent steps disclosed in Chatterjee et al. are different in a number of respects from the steps in the present methods.
Anthony, U.S. Pat. No. 4,499,655, is directed to a method that is somewhat similar to the present invention in its usage, but the method of forming the feedthroughs in the substrate is different: hole drilling is used in Anthony. This method cannot be used for small geometries. In this prior patent also, silicon is not a substrate of primary interest; rather, sapphire is utilized. Anthony also does not mention an insulating/coating layer inside the feedthroughs, as in the present invention, since Anthony assumes an insulating substrate body.
El-Kareh et al., in U.S. Pat. No. 4,725,562, describes a way of making contact to a device that has trench isolation. This is basically an "IC processing"-type patent relating to the performance of individual transistors in an IC and it does not relate significantly to the method, technique or functionality of the present invention.
From the above, it will be apparent that a need continues to exist for methods that will provide a connector for packaging that can accommodate large numbers of I/O leads. Moreover, there remains a need for methods of forming feedthroughs in silicon wafers that are reliable and reproducible.